Display panels

ABSTRACT

Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of pending U.S. patent application Ser.No. 11/456,596, filed Jul. 11, 2006, the entirety of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to display devices, and in particular to a displaypanel capable of reducing number of data signal driving IC.

2. Description of the Related Art

FIG. 1 is a diagram showing a conventional display driving circuit 10.It includes two data drivers 121 and 122, a scan driver 11, a pixelmatrix comprising display cells 13, and switches 161 and 162 comprisingtransistors. Each display cell 13 in the odd columns of the pixel matrixreceives a data signal through a data line 151 from the data driver 121or 122. Each display cell 13 in the even columns of the pixel matrixreceives a data signal through a data line 152 from the data driver 121or 122. The display cells 13 also receive scan signals through scanlines 14 from the scan driver 11. To reduce number of the data drivers,data lines 151 and 152 are respectively coupled to the display cells 13in the odd and even column of the pixel matrix share the same dataterminal as the data driver through the switches 161 and 162 controlledby signals SW1 and SW2. When one of the scan signals is applied, the oddand even display cells 13 in the scanned row of the matrix receive thedata signal output from the same terminal of the data driver 121 or 122by turns. In FIG. 1, for example, the number of the data drivers is halfthat when not using the switches to share the data terminals since eachdata terminal provides the data signals to two columns of display cellsof the pixel matrix.

However, in the conventional display driving circuit, the switchingfrequency of the switches 161 and 162 is n times the frame rate, whereinn is the number of the columns in the pixel matrix. For example, theswitching frequency of the switches in a display having 768 pixelcolumns and a frame rate of 60 Hz is 46080 Hz. Such a switchingfrequency is much higher than that of the thin-film transistors (TFTs)used in the display cells 13. Besides, the high duty ratio and highcurrent stress also degrades the reliability of the circuit.

BRIEF SUMMARY OF THE INVENTION

A detailed description is given in the following embodiments withreference to the accompanying drawings.

Embodiments of display panels are provided, in which a data driveroutputs first, second, third and fourth data signals in sequence througha data line, a scan driver outputs first and second scan signals insequence through first and second scan lines and an auxiliary drivergenerates first and second auxiliary signals in sequence. First andsecond display cells receive the first scan signal through the firstscan line simultaneously and receive the first and the second datasignals through the data line respectively, and a first switch iscoupled to the data line and the second display cell, turning on and offin sequence according to the first auxiliary signal when the first scansignal is applied thereto such that the second display cell receives thefirst data signal and the first display cell receives the second datasignal in sequence.

The invention also provides embodiments of a display panel, in which adata driver outputs first, second, third and fourth data signals insequence through a data line, and first and second scan drivers outputfirst and second scan signals in sequence through first and second scanlines. First and second display cells receive the first scan signalthrough the first scan line and the second scan line respectively andreceive the first and the second data signal respectively through thedata line simultaneously.

The invention also provides embodiments of electronic device, in whichthe disclosed display system is applied and a power supply powers thedisplay system to display images.

The invention also provides embodiments of a driving method, in which afirst auxiliary signal is applied to turn on a first switch such that afirst data signal from a data line is transferred to first and seconddisplay cells and a first scan signal is applied to enable the first andthe second display cells to receive the first data signal, during afirst period. The first auxiliary signal is de-asserted to turn off thefirst switch such that the first display cell is electrically separatedfrom the data line and the second display cell receives a second datasignal from the data line according to the first scan signal, during asecond period, in which the first switch is turned off until the firstscan signal and the first auxiliary signal are applied at the same timeagain. A second auxiliary signal is applied to turn on a second switchsuch that a third data signal from the data line is transferred to thirdand fourth display cells and a second scan signal is applied to enablethe third and the fourth display cells to receive the third data signal,during a third period. The second auxiliary signal is de-asserted toturn off the second switch such that the third display cell iselectrically separated from the data line and the fourth display cellreceives a fourth data signal from the data line according to the secondscan signal, during a fourth period, in which the second switch isturned off until the second scan signal and the second auxiliary signalare applied at the same time again.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 shows a conventional display driving circuit;

FIG. 2A shows an embodiment of a display panel of the invention;

FIG. 2B is a timing chart of the display panel shown in FIG. 2A;

FIG. 3A shows another embodiment of display panel of the invention;

FIG. 3B is a timing chart of the display panel shown in FIG. 3A; and

FIG. 4 is a schematic view showing an electronic device using displaypanels shown in FIGS. 2A and 3A.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 2A is a diagram showing a display panel 200A according to a firstembodiment of the invention. It includes a data driver 21, a scan driver22, an auxiliary driver 23, a timing controller 24, and a pixel matrixcomposed of six (for example) display cells P1˜P6, and three switchesST1, ST2 and ST3. For example, the display panel 200A can be a liquidcrystal display panel, a plasma display panel or an organic lightemitting display panel, but is not limited thereto.

The data driver 21 outputs the desired data signals (not shown) for thesix display cells P1˜P6 through the data line DL. For example, the datadriver 21 can be a data driving integrated circuit (IC) formed bysingle-crystal Si transistors, but is not limited thereto. The scandriver 22 outputs scan signals S1˜S3 in sequence through the scan linesSL1˜SL3. For example, the scan driver 22 can also be a scan drivingintegrated circuit (IC) formed by single-crystal Si transistors. Theauxiliary driver 23 outputs auxiliary signals SW1˜SW3 through auxiliarysignal lines AL1˜AL3. In the embodiment, the auxiliary driver 23 is adriving integrated circuit (IC) formed by a-Si transistors on thedisplay panel rather than single-crystal Si transistors, and the datadriver 21, the scan driver 22 and the auxiliary driver 23 are controlledby the timing controller 24.

The display cells P1 and P2 receive the scan signal 51 through the scanline SL1 simultaneously, the display cells P3 and P4 receive the scansignal S2 through the scan line SL2 simultaneously, and the displaycells P5 and P6 receive the scan signal S3 through the scan line SL3simultaneously. The display cells P1, P3 and P5 receive correspondingdata signals respectively through the data line DL simultaneously, thedisplay cells P2, P4 and P6 coupled to the switches ST1, ST2 and ST3respectively, receiving corresponding data signals respectively throughthe data line DL simultaneously. The switches ST1, ST2 and ST3 arecoupled between the data line DL and the display cell P2, between thedata line DL and the display cell P4 and between the data line DL andthe display cell P6 respectively.

As shown, the display cell P1 comprises a transistor M1 and a capacitorCs1, the display cell P2 comprises a transistor M2 and a capacitor Cs2,and the display cells P3˜P6 are similar to the display cells P1 and P2.Gates of the transistor M1, M3 and M5 are coupled to the scan lines SL1,SL2 and SL3 respectively, drains of which are coupled to the data lineDL, and sources of which are coupled to capacitors Cs1, Cs3 and Cs5respectively. Gates of the transistors M2, M4 and M6 are coupled to thescan lines SL1, SL2 and SL3 respectively, drains of which are coupled tothe data line DL, and sources of which are coupled to capacitors Cs2,Cs4 and Cs6 respectively.

The switches ST1˜ST3 are formed by transistors M7˜M9, gates of thetransistors M7˜M9 are coupled to the auxiliary signals SW1˜SW3respectively, drains of which are coupled to the data line DL, sourcesof which are coupled to the display cells P2, P4 and P6 respectively. Inthe embodiment, the transistors M1˜M9 are a-Si transistors, but are notlimited thereto.

FIG. 2B is a timing chart of the display panel shown in FIG. 2A. Thescan period when the scan signal S1 is applied (the scan signal S1 isasserted and has a logic high level) is divided into two sub-periods T1and T2. The auxiliary signal SW1 turns on the transistor M7 (closes theswitch ST1) and turns off the transistor M7 (the switch ST1 is opened)in sequence during the sub-periods T1 and T2 respectively, when the scansignal S1 is applied.

During the sub-period T1, during which the transistor M7 is turned on,the display cell P2 in the even column of the pixel matrix receives thedata signal from the data driver 21 through the data line DL, and thedisplay cell P1 in the odd column of the pixel matrix receives the datasignal from the data driver 21 through the data line DL during thesub-period T2, during which the transistor M7 is turned off. Forexample, the data signal from the data driver 21 during the sub-periodT1 can be a data signal with a positive polarity, and the data signalfrom the data driver 21 during the sub-period T2 can be a data signalwith negative polarity, but are not limited thereto.

It should be noted that the display cell P1 can also receive the datasignal for the display cell P2 during sub-period T1, but the data signalreceived by the display cell P1 is updated by the data signal on thedata line DL during the sub-period T2. Further, during the period (T1and T2), during which the scan signal S1 is applied, the switch ST1 onlyturns on and off once according to the auxiliary signal SW1 until thescan signal S1 is applied thereto again. Namely, the transistor M7 isturned off during the sub-period T2 and on again when the auxiliarysignal SW1 is applied thereto again.

Next, when the scan signal S1 is de-asserted and the scan signal S2 isapplied (has a logic high level), the transistors M1, M2 and M7 areturned off. The scan period when the scan signal S2 is applied anddivided into two sub-periods T3 and T4. The auxiliary signal SW2 turnson the transistor M8 (closes the switch ST2) and turns off thetransistor M8 (the switch ST2 is opened) in sequence during thesub-periods T3 and T4 respectively, when the scan signal S2 is applied.

During the sub-period T3, during which the transistor M8 is turned on,the display cell P4 in the even column of the pixel matrix receives thedata signal from the data driver 21 through the data line DL, and thedisplay cell P3 in the odd column of the pixel matrix receives the datasignal from the data driver 21 through the data line DL during thesub-period T4, during which the transistor M8 is turned off. Forexample, the data signal from the data driver 21 during the sub-periodT3 can be a data signal with a positive polarity, and the data signalfrom the data driver 21 during the sub-period T4 can be a data signalwith negative polarity, but are not limited thereto.

It should be noted that the display cell P3 can also receive the datasignal for the display cell P4 during sub-period T3, but the data signalreceived by the display cell P3 is updated by the data signal on thedata line DL during the sub-period T4. Further, during the period (T3and T4), during which the scan signal S2 is applied, the switch ST2 onlyturns on and off once according to the auxiliary signal SW2 until thescan signal S2 is applied thereto again. Namely, the transistor M8 isturned off during the sub-period T4 and on again when the auxiliarysignal SW2 is applied thereto again.

Similarly, when the scan signal S2 is de-asserted and the scan signal S3is applied (has a logic high level), the transistors M3, M4 and M8 areturned off. The scan period when the scan signal S3 is applied isdivided into two sub-periods T5 and T6. The auxiliary signal SW3 turnson the transistor M9 (closes the switch ST3) and turns off thetransistor M9 (the switch ST3 is opened) in sequence during thesub-periods T5 and T6 respectively, when the scan signal S3 is applied.

During the sub-period T5, during which the transistor M9 is turned on,the display cell P6 in the even column of the pixel matrix receives thedata signal from the data driver 21 through the data line DL, and thedisplay cell P5 in the odd column of the pixel matrix receives the datasignal from the data driver 21 through the data line DL during thesub-period T6, during which the transistor M9 is turned off. Forexample, the data signal from the data driver 21 during the sub-periodT5 can be a data signal with a positive polarity, and the data signalfrom the data driver 21 during the sub-period T6 can be a data signalwith negative polarity, but are not limited thereto.

It should be noted that the display cell P5 can also receive the datasignal for the display cell P6 during sub-period T5, but the data signalreceived by the display cell P5 is updated by the data signal on thedata line DL during the sub-period T6. Further, during the period (T5and T6), during which the scan signal S3 is applied, the switch ST3 onlyturns on and off once according to the auxiliary signal SW3 until thescan signal S3 is applied thereto again. Namely, the transistor M9 isturned off during the sub-period T6 and would be turned on again whenthe auxiliary signal SW3 is applied thereto again.

Namely, during a frame period, during which all the scan lines arescanned in sequence once, the auxiliary signals SW1˜SW3 are only appliedin sequence once such that switches ST1˜ST3 are each switched once.Thus, the switching frequency of the switches ST1˜ST3 is lowered to theframe rate, which eliminates the reliability issue in the conventionaldisplay panel.

The invention also provides a driving method for the display panel shownin FIG. 2A.

During a period T1, an auxiliary signal SW1 is applied to turn on aswitch ST1 such that a data signal from a data line DL is transferred todisplay cells P1 and P2 and a scan signal S1 is applied to enable thedisplay cells P1 and P2 to receive the data signal on the data line DL.

During a period T2, the auxiliary signal SW1 is de-asserted to turn offthe switch ST1 such that the display cell P2 is electrically separatedfrom the data line DL and the display cell P1 receives a data signalfrom the data line DL according to the scan signal S1, in which thewitch ST1 is turned off until the scan signal S1 and the auxiliarysignal SW1 are applied thereto again.

During a period T3, an auxiliary signal SW2 is applied to turn on aswitch ST2 such that a data signal from the data line DL is transferredto display cells P3 and P4 and a scan signal S2 is applied to enable thedisplay cells P3 and P4 to receive the data signal on the data line DL.

During a period T4, the auxiliary signal SW2 is de-asserted to turn offthe switch ST2 such that the display cell P4 is electrically separatedfrom the data line DL and the display cell P3 receives a data signalfrom the data line DL according to the scan signal S2, in which theswitch ST2 is turned off until the scan signal S2 and the auxiliarysignal SW2 are applied thereto again.

During a period T5, an auxiliary signal SW3 is applied to turn on aswitch ST3 such that a data signal from the data line DL is transferredto display cells P5 and P6 and a scan signal S3 is applied to enable thedisplay cells P5 and P6 to receive the data signal on the data line DL.

During a period T6, the auxiliary signal SW3 is de-asserted to turn offthe switch ST3 such that the display cell P6 is electrically separatedfrom the data line DL and the display cell P5 receives a data signalfrom the data line DL according to the scan signal S3, in which theswitch ST3 is turned off until the scan signal S3 and the auxiliarysignal SW3 are applied thereto again.

Namely, during a frame period, during which all the scan lines arescanned in sequence once, the auxiliary signals SW1˜SW3 are only appliedin sequence once such that the switches are ST1˜ST3 each switched once.Thus, the switching frequency of the switches ST1˜ST3 is lowered to theframe rate, which eliminates the reliability issue in the conventionaldisplay panel.

FIG. 3A shows another embodiment of a display panel 200B of theinvention. It comprises a data driver 41, two scan driver 42A and 42B, atiming controller 43, and a pixel matrix composed of eight (for example)display cells P21˜P28. For example, the display panel 200B can be aliquid crystal display panel, a plasma display panel or an organic lightemitting display panel, but it is not limited thereto.

The data driver 41 outputs the desired data signals (not shown) for theeight display cells P21˜P28 through data lines DL1 and DL2. For example,the data driver 41 can be a data driving integrated circuit (IC) formedby single-crystal Si transistors, but it is not limited thereto.

The data driver 41, the two scan drivers 42A and 42B are controlled bythe timing controller 43. For example, the timing controller 43 providesa first set of control signals such as clock signals CK1 and /CK1 andenabling signal DS1 (as shown in FIG. 3B) to the scan driver 42A and asecond set of controls signals such as clock signals CK2 and /CK2 andenabling signal DS2 (as shown in FIG. 3B) to the scan driver 42B.

The scan drivers 42A and 42B generate scan signals S1˜S4 in sequenceaccording to the first and second sets of control signals, and the scandriver 42A outputs the scan signals 51 and S3 through the scan lines SL1and SL3 respectively and the scan driver 42B outputs the scan signals S2and S4 through the scan lines SL2 and SL4 respectively. Namely, the scansignals S2 and S4 are not generated according to the scan signals 51 andS3, but generated by different scan drivers. In the embodiment, the scandriver 42A and 42B can also be a driving integrated circuit (IC) formedby a-Si transistors on the display panel rather than single-crystal Sitransistors.

The display cells P21 and P22 receive the scan signal 51 through thescan line SL1 simultaneously, the display cells P23 and P24 receive thescan signal S2 through the scan line SL2 simultaneously, the displaycells P25 and P26 receive the scan signal S3 through the scan line SL3simultaneously, and the display cells P27 and P28 receive the scansignal S4 through the scan line SL4 simultaneously. The display cellsP21, P23, P25 and P27 receive corresponding data signals respectivelythrough the data line DL1 simultaneously, the display cells P22, P24,P26 and P28 receive corresponding data signals respectively through thedata line DL2 simultaneously.

As shown, each display cell P21˜P28 comprises a transistor, a storagecapacitor and a liquid element, and the transistors in the display cellsP21˜P28 can be a-Si transistors, but are not limited thereto.

FIG. 3B is a timing chart of the display panel shown in FIG. 3A. Duringa period T21, a scan signal 51 is applied (the scan signal is assertedand has a logic high level), and the display cells P21 and P22 in theodd column of the pixel matrix receives the data signals from the datadriver 41 through the data lines DL1 and DL2.

During a period T22, a scan signal S2 is applied, and the display cellsP23 and P24 in the even column of the pixel matrix receives the datasignals from the data driver 41 through the data lines DL1 and DL2.

During a period T23, a scan signal S3 is applied, and the display cellsP25 and P26 in the odd column of the pixel matrix receive the datasignals from the data driver 41 through the data lines DL1 and DL2.

During a period T24, a scan signal S4 is applied, and the display cellsP27 and P28 in the even column of the pixel matrix receive the datasignals from the data driver 41 through the data lines DL1 and DL2. Forexample, the data signals output from the data driver 41 during theperiods T21 and T23 can be data signals with a positive polarity andthat output from the data driver 41 during the period T22 and T24 can bedata signals with a negative polarity, but are not limited thereto.

Namely, all scan lines of the display panel 200B are scanned in sequenceby the scan drivers 42A and 42B, and display cells in two columns shareone data line to receive data signals from the data driver. As theswitching frequency of the switches ST1˜ST3 is lowered to the framerate, the reliability issue in the conventional display panel can beeliminated.

FIG. 4 is a schematic view showing an electronic device using displaysystems shown in FIGS. 2A and 3A. As shown, the electronic device 300comprises a housing 210, the display panel 200A/200B, and power supply220. The power supply 220 is operationally coupled to the display panels200A/200B to powers the display panel 200A/200B to display images. Forexample, the display panel 200A/200B can be a liquid crystal displaypanel, a plasma display panel or an organic light emitting displaypanel, and the electronic device 300 can be a PDA, a display monitor, anotebook computer, a table computer or a cellular phone.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

1. A display panel, comprising: a data line; a first and second scanlines; a data driver for outputting a first, second, third and fourthdata signals in sequence through the data line; a first and second scandrivers for outputting a first and second scan signals in sequencethrough the first and the second scan lines; and a first and seconddisplay cells for receiving the first scan signal and the second scansignal through the first scan line and the second scan linerespectively, and receiving the first and the second data signal,respectively, through the data line commonly.
 2. The display panel asclaimed in claim 1, wherein the first scan driver and the second scandriver are adapted to a timing controller which generates a first andsecond sets of control signals, the first scan driver generates thefirst scan signal according to the first set of control signals, and thesecond scan driver generates the second scan signal according to thesecond set of control signals.
 3. The display panel as claimed in claim1, further comprising a timing controller generating a first and asecond sets of control signals, wherein the first scan driver generatesthe first scan signal according to the first set of control signals, andthe second scan driver generates the second scan signal according to thesecond set of control signals.
 4. The display panel as claimed in claim2, wherein the data driver comprises a driving integrated circuit (IC)formed by single-crystal Si.
 5. The display panel as claimed in claim 2,wherein the first and second scan drivers comprise single-crystal Si. 6.An electronic device, comprising: a display panel as claimed in claim 1;and a power supply for powering the display panel to display images.